1. Field of the Invention
Generally, the present disclosure relates to the field of fabrication of integrated circuits, and, more particularly, to semiconductor devices having conductive lines, such as gate electrodes of field effect transistors, which are formed on a pronounced surface topography.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features are steadily decreased to enhance device performance and functionality. One important circuit element in complex integrated circuits is a field effect transistor, which represents a component having a channel region, whose conductivity may be controlled by an electric field that is generated by applying a control voltage to a gate electrode formed near the channel region and separated therefrom by a gate insulation layer. The channel region is generally defined by respective PN junctions formed by an interface of highly doped drain and source regions and an inversely doped region located between the drain and source regions. Important characteristics for the performance of an integrated circuit are, among others, the switching speed of the individual transistor elements and the drive current capability. Thus, one important aspect for obtaining a high transistor performance is the reduction of the overall resistance of the current path defined by the channel region, the resistance of the drain and source regions and the respective contacts that connect the transistor with peripheral devices, such as other transistors, capacitors and the like. The reduction of the channel length thus provides reduced resistance of the channel region and also offers the potential to increase the packing density of the integrated circuit. Upon reducing the transistor dimension, the transistor width is typically also reduced in view of packing density and switching speed, which may, however, reduce the drive current capability. It is therefore of great importance to reduce the series resistance of a transistor for given design dimensions as much as possible so as to combine moderately high drive current capability with increased switching speed for sophisticated logic circuits.
Hence, it has become an important design target to increase the conductivity of lines and contact regions, such as drain and source regions, gate electrodes, polysilicon interconnect lines and the like, since the cross-sectional area of these lines and regions is also reduced as the general transistor dimensions are decreased. The cross-sectional area, however, determines, in combination with the characteristics of the material comprising the conductive lines and contact regions, the resistance of the respective line or contact region. As a result, in highly scaled semiconductor devices, the conductive lines and contact regions may exhibit a higher resistance unless the reduced cross-section is compensated for by improving the electrical characteristics of the material forming the lines and contact regions, such as the gate electrode, and the drain and source contact regions.
Hence, in combination with precisely defining the gate electrodes or other conductive lines in the device level, it is also of great importance to improve the characteristics of conductive regions that are substantially comprised of semiconductor material such as silicon. For instance, in modern integrated circuits, the individual semiconductor devices, such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by polysilicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminum by, for example, copper and copper alloys, process engineers are confronted with a challenging task when an improvement in the electrical characteristics of silicon-containing semiconductor lines and semiconductor contact regions is required.
In some approaches, some structural aspects may be realized in a transistor architecture to achieve a significant improvement in one or more of the above aspects. For instance, in modern semiconductor devices, silicon-on-insulator (SOI) architecture may frequently be used due to some inherent advantages of an SOI transistor with respect to a bulk device, such as reduced junction capacity, increased degree of insulation to neighboring devices and the like. Furthermore, in SOI devices, isolation trenches are typically provided, which in some approaches may not be refilled with an insulating material prior to the gate patterning in order to obtain, in addition to a process flow of reduced complexity, significant advantages with respect to increased drive current capability. For example, due to the missing fill material in the isolation trenches during the gate patterning process, the gate insulation material and the gate electrode material may also be formed at the end portions of the gate electrode with respect to the transistor width direction, thereby enabling the creation of the conductive channel in a highly efficient manner across the entire width dimension of the transistor. Consequently, an efficient charge carrier transport may occur even at the end portions, which, in devices having a filled isolation trench, may be significantly reduced at these channel areas due to a reduced capacitive coupling to the gate electrode. Similarly, in a respective configuration with a missing insulating material at this manufacturing stage, which is also referred to as “mesa isolation,” the formation of metal silicides, provided for increasing the conductivity of the semiconductor material, may be enhanced at these end portions of the channel, thereby also reducing the overall series resistance of the transistor.
Although a plurality of advantages may be associated with the above-described approach, the precise patterning of the gate electrode may be significantly compromised by the corresponding pronounced surface topography of the device surface prior to and during the patterning process, in particular when highly scaled transistors are considered. As is well known, optical lithography processes rely on the characteristics of the imaging process for transferring an image into a resist material in order to form a latent image in the resist material, which may then be developed to obtain a resist mask, on the basis of which the gate electrode material may be patterned. For highly sophisticated applications, however, any surface variations may have a negative influence, since, for instance, the depth of focus of modern lithography tools is typically reduced with a reduction of exposure wavelength. Moreover, the resist materials for reduced exposure wavelength may have to be provided with reduced thickness, thereby also increasing the sensitivity to the surface topography. Hence, the potential advantages provided by the above-described process flow for forming a mesa isolation may be partially or completely offset by process non-uniformities during the patterning of the gate electrodes, in particular for highly scaled devices, thereby rendering the conventional mesa isolation approach less attractive.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.